AS4C2M32SA-6TINTR

Alliance Memory
913-AS4C2M32SA6TINTR
AS4C2M32SA-6TINTR

Mfr.:

Description:
DRAM SDRAM,64M,3.3V 166MHz,2M x 32

ECAD Model:
Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

Availability

Stock:
0

You can still purchase this product for backorder.

Factory Lead Time:
20 Weeks Estimated factory production time.
Minimum: 1   Multiples: 1
Unit Price:
£-.--
Ext. Price:
£-.--
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 1000)

Pricing (GBP)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™
£4.28 £4.28
£3.99 £39.90
£3.87 £96.75
£3.77 £188.50
£3.68 £368.00
£3.57 £892.50
£3.48 £1,740.00
Full Reel (Order in multiples of 1000)
£3.35 £3,350.00
£3.31 £6,620.00
† A MouseReel™ fee of £3.50 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable.

Alternative Packaging

Mfr. Part No.:
Packaging:
Tray
Availability:
In Stock
Price:
£5.25
Min:
1

Product Attribute Attribute Value Select Attribute
Alliance Memory
Product Category: DRAM
RoHS:  
SDRAM
64 Mbit
32 bit
166 MHz
TSOP-II-86
2 M x 32
5.4 ns
3 V
3.6 V
- 40 C
+ 85 C
AS4C2M32SA
Reel
Cut Tape
MouseReel
Brand: Alliance Memory
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: TW
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 1000
Subcategory: Memory & Data Storage
Supply Current - Max: 95 mA
Products found:
To show similar products, select at least one checkbox
Select at least one checkbox above to show similar products in this category.
Attributes selected: 0

CNHTS:
8542319090
USHTS:
8542320002
JPHTS:
854232021
MXHTS:
8542320201
ECCN:
EAR99

AS4C SDRAM

Alliance Memory AS4C SDRAM is high-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.